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For Students and Instructors First Edition
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Table of Contents
Tools (includes ARCTools software)
VHDL description of ARC
Practice problems with solutions
Author: Miles Murdocca
Author: Vincent Heuring
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Computer Architecture and Organization: An Integrated Approach

Miles J. Murdocca and Vincent P. Heuring, John Wiley & Sons, (2007)

Table of Contents


1. Introduction

1.1. Overview
1.2. A Brief History of Computing
1.3. The Von Neumann Model
1.4. The System Bus Model
1.5. Levels of Machines
1.5.1. Upward Compatibility
1.5.2. The Levels
1.6. A Typical Computer System
1.7. Role of the Network
1.8. Organization of the Book
1.9. Case Study: What Happened to Supercomputers?

2. Data Representation

2.1. Introduction
2.2. Fixed Point Numbers
2.2.1. Range and Precision in Fixed Point Numbers
2.2.2. The Associative Law of Algebra Does Not Always Hold in Computers
2.2.3. Radix Number Systems
2.2.4. Conversions Among Radices
2.2.5. An Early Look at Computer Arithmetic
2.2.6. Signed Fixed Point Numbers
2.3. Floating Point Numbers
2.3.1. Range and Precision In Floating Point Numbers
2.3.2. Normalization, and The Hidden Bit
2.3.3. Representing Floating Point Numbers in the Computer--Preliminaries
2.3.4. Error in Floating Point Representations
2.3.5. The IEEE 754 Floating Point Standard
2.4. Case Study: Patriot Missile Defense Failure Caused by Loss of Precision
2.5. Character Codes
2.5.1. The ASCII Character Set
2.5.2. The EBCDIC Character Set
2.5.3. The Unicode Character Set

3. Arithmetic

3.1. Overview
3.2. Fixed Point Addition and Subtraction
3.2.1. Two's complement addition and subtraction
3.2.2. Sign Extension
3.2.3. Hardware implementation of adders and subtractors
3.2.4. One's Complement Addition and Subtraction
3.3. Fixed Point Multiplication and Division
3.3.1. Unsigned Multiplication
3.3.2. Unsigned Division
3.3.3. Signed Multiplication and Division
3.4. Floating Point Arithmetic
3.4.1. Floating Point Addition and Subtraction
3.4.2. Floating Point Multiplication and Division
3.5. High Performance Arithmetic
3.5.1. High Performance Addition
3.5.2. High Performance Multiplication
3.5.3. High Performance Division
3.5.4. Residue Arithmetic

4. The Instruction Set Architecture

4.1. Hardware Components of the Instruction Set Architecture
4.1.1. The System Bus Model Revisited
4.1.2. Memory
4.1.3. The CPU
4.2. ARC, A RISC Computer
4.2.1. ARC Memory
4.2.2. ARC Registers
4.2.3. ARC Assembly Language Format
4.2.4. The ARC instruction set
4.2.5. ARC Instruction Formats
4.2.6. SPARC and ARC Data Formats
4.2.7. ARC Instruction Descriptions
4.3. Pseudo-Ops
4.4. Synthetic Instructions
4.5. Examples of Assembly Language Programs
4.5.1. Variations in machine architectures and addressing
4.5.2. Performance of Instruction Set Architectures
4.6. Accessing Data in Memory--Addressing Modes
4.7. Subroutine Linkage and Stacks
4.8. Input and Output in Assembly Language
4.9. Case Study: The Java Virtual Machine ISA

5. Datapath and Control

5.1. Basics of the Microarchitecture
5.2. The Datapath
5.2.1. Datapath Overview
5.3. The Control Section - Microprogrammed
5.3.1. Timing
5.3.2. Developing the Microprogram
5.3.3. Traps and Interrupts
5.3.4. Nanoprogramming
5.4. The Control Section - Hardwired
5.5. Case Study: The VHDL Hardware Description Language
5.5.1. Background
5.5.2. What is VHDL?
5.5.3. A VHDL specification of the Majority Function
5.5.4. 9-Value logic system
5.6. Case Study: What Happens When a Computer Boots Up?

6. Languages and the Machine

6.1. The Compilation Process
6.1.1. Steps in compilation
6.1.2. The Compiler Mapping Specification
6.1.3. How the compiler maps the three instruction Classes into Assembly Code
6.1.4. Data movement
6.1.5. Arithmetic instructions
6.1.6. Program Control flow
6.2. The Assembly Process
6.2.1. Assembly and two pass assemblers
6.2.2. Assembly and the symbol table
6.2.3. Final tasks of the assembler
6.2.4. Programs for embedded vs. virtual memory systems
6.3. Linking and Loading
6.3.1. Linking
6.3.2. Resolving external references
6.3.3. Loading
6.4. Macros
6.5. Quantitative Analyses of Program Execution
6.5.1. Quantitative performance analysis
6.6. From CISC to RISC
6.7. Pipelining the Datapath
6.7.1. Arithmetic, branch, and load-store instructions
6.7.2. Pipelining instructions
6.7.3. Keeping the pipeline Filled
6.8. Overlapping Register Windows
6.9. Low Power Coding

7. Memory

7.1. Overview
7.2. The Memory Hierarchy
7.3. Random Access Memory
7.4. Memory Chip Organization
7.4.1. Constructing Large RAMS from Small RAMS
7.4.2. Commercial Memory Modules
7.4.3. Read-Only Memory
7.4.4. Flash Memory
7.5. Case Study: Rambus Memory
7.6. Cache Memory
7.6.1. Associative Mapped Cache
7.6.2. Direct Mapped Cache
7.6.3. Set Associative Mapped Cache
7.6.4. Cache performance
7.6.5. Hit Ratios and Effective Access Times
7.6.6. Multilevel Caches
7.6.7. Cache management
7.6.8. Cache Coherency
7.7. Virtual Memory
7.7.1. Overlays
7.7.2. Paging
7.7.3. Segmentation
7.7.4. Protection
7.7.5. Fragmentation
7.7.6. The Translation Lookaside Buffer
7.7.7. Putting it all Together: Virtual Memory, Main memory, Cache Memory, Translation Lookaside Buffer
7.8. Advanced Topics
7.8.1. Content-Addressable (Associative) Memories
7.9. Case Study: Associative Memory in Routers
7.10. Case Study: The Intel Pentium 4 Memory System

8. Buses and Peripherals

8.1. Parallel Bus Architectures
8.1.1. Bus Structure, Protocol, and Control
8.1.2. Bus Clocking
8.1.3. The Synchronous Bus
8.1.4. The Asynchronous Bus
8.1.5. Bus Arbitration--Masters and Slaves
8.2. Bridge-Based Bus Architectures
8.3. Internal Communication Methodologies
8.3.1. Programmed I/O
8.3.2. Interrupt-driven I/O
8.3.3. Direct Memory Access (DMA)
8.4. Case Study: Communication on the Intel Pentium Architecture
8.4.1. System clock, bus clock, and bus speeds
8.4.2. Address, data, memory, and I/O capabilities
8.4.3. Data words have soft-alignment
8.4.4. Bus cycles in the Pentium family
8.4.5. Memory read and write bus cycles
8.4.6. The burst Read bus cycle
8.4.7. Bus hold for request by bus master
8.4.8. Data transfer rates
8.5. Serial Bus Architectures
8.5.1. RS-232
8.5.2. UniversAL Serial Bus (USB)
8.5.3. Firewire
8.6. Mass Storage
8.6.1. Magnetic Disks
8.6.2. Magnetic Tape
8.6.3. Optical Disks
8.7. RAID - Redundant Arrays of Inexpensive Disks
8.8. Input Devices
8.8.1. Keyboards
8.8.2. Tablets
8.8.3. Mice and Trackballs
8.8.4. Touch Sensitive Pen Based Display
8.8.5. Joysticks
8.9. Output Devices
8.9.1. Laser Printers
8.9.2. Video Displays
8.9.3. Liquid Crystal Displays (LCDs)
8.10. Case Study: Graphics Processing Unit
8.11. Case Study: How a Virus Infects a Machine

9. Networking and Communication

9.1. A Few Modulation Schemes
9.2. Transmission Media
9.2.1. Two-Wire Open Lines
9.2.2. Twisted-Pair Lines
9.2.3. Coaxial Cable
9.2.4. Optical Fiber
9.2.5. Satellites
9.2.6. Terrestrial Microwave
9.2.7. Radio
9.3. Error Detection and Correction
9.3.1. Bit Error Rate Defined
9.3.2. Hamming Codes
9.3.3. Vertical Redundancy Checking
9.3.4. Cyclic Redundancy Checking
9.4. Networking and Network Device Architectures
9.4.1. The OSI Model
9.4.2. Topologies
9.4.3. Ethernet
9.4.4. Hubs, Bridges, Switches, Routers, and Gateways
9.5. Storage Area Networks
9.6. Case Study: Cisco Router Architecture

10. Advanced Computer Architecture

10.1. Parallel Architecture
10.1.1. Measuring Performance
10.1.2. The Flynn Taxonomy
10.1.3. Interconnection Networks
10.1.4. Mapping an Algorithm onto a Parallel Architecture
10.2. Superscalar Machines, and the PowerPC
10.2.1. Instruction Set Architecture of the PowerPC
10.2.2. Hardware architecture of the PowerPC
10.3. VLIW Machines, and the Itanium
10.3.1. Case Study: The Intel IA-64 (Itanium) Architecture
10.3.2. Background--the 80x86 Cisc architecture
10.3.3. The Itanium: an epic architecture
10.4. Case Study: Extensions to the Instruction Set - The Intel MMX/SSEx and Motorola AltiVec SIMD Instructions
10.4.1. Background
10.4.2. The Base Architectures
10.4.3. Vector Registers
10.4.4. Vector Arithmetic operations
10.4.5. Vector compare operations
10.4.6. Case Study Summary
10.5. Programmable Logic Devices and Custom ICs
10.5.1. The Role of CAD Tools in PLD Design
10.5.2. PLAs and PALs
10.5.3. Complex Programmable Logic Devices
10.5.4. Field-Programmable Gate Arrays
10.5.5. Application-Specific Integrated Circuits
10.6. Unconventional Architectures
10.6.1. DNA Computing
10.6.2. Quantum Computing
10.6.3. Multi-Valued Logic
10.6.4. Neural Networks

Appendix A: Digital Logic

A.1. Introduction
A.2. Combinational Logic
A.3. Truth Tables
A.4. Logic Gates
A.4.1. Electronic implementation of logic gates
A.4.2. Tri-State Buffers
A.5. Properties of Boolean Algebra
A.6. The Sum-of-Products Form, and Logic Diagrams
A.7. The Product-of-Sums Form
A.8. Positive vs. Negative Logic
A.9. The Data Sheet
A.10. Digital Components
A.10.1. Levels of Integration
A.10.2. Multiplexers
A.10.3. Demultiplexers
A.10.4. Decoders
A.10.5. Priority Encoders
A.10.6. Programmable Logic Arrays
A.11. Sequential Logic
A.11.1. The S-R Flip-Flop
A.11.2. The Clocked S-R Flip-Flop
A.11.3. The D Flip-Flop and the Master-Slave Configuration
A.11.4. J-K and T Flip-Flops
A.12. Design of Finite State Machines
A.13. Mealy vs. Moore Machines
A.14. Registers
A.15. Counters
A.16. Reduction of Combinational Logic and Sequential Logic
A.17. Reduction of Two-Level Expressions
A.17.1. The Algebraic Method
A.17.2. The K-Map Method
A.17.3. The Tabular Method
A.17.4. Logic reduction: Effect on speed and performance
A.18. State Reduction

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© 2009 Miles J. Murdocca and Vincent P. Heuring