COMPUTER ARCHITECTURE AND ORGANIZATION: AN INTEGRATED APPROACH, 1/e -- ERRATA
Last updated: 30 April 2014
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(1) Figure 1-11 covering Moore's Law has an empty box in the middle of the
chart. The box should be replaced with "Intel Processor Line" and should
appear below the plot, not on top of it.
(2) In section 4.2.3, on page 105 in the first paragraph under "The ARC
Arithmetic and Logic Instructions", there is a reference to an example
assembly instruction in Fig. 4-8 labeled "lab_3". There is no corresponding
instruction in the figure.
(3) Page 107, Figure 4-10: The last instruction is:
"st %r3 [z]"
It should have a comma between arguments:
"st %r3, [z]"
[Thanks to Nick Sorrell, University of Cincinnati]
(4) On page 108 there are references to the "bz" and "bnz" instructions in
several places (e.g., fig. 4-11 as well as the first full paragraph). These
appear to be inconsistent with the use of "be" and "bne" later in the chapter.
The latter are the correct mnemonics for the book as they are also the ones
the ARCTools simulator recognizes. However, bz and bnz are equivalent to be
and bne in the SPARC.
(5) Page 118, Table 4.7: The Field ID for simm13 should be 0xABB, and the
corresponding object code should be 0101010101011 (13 bits). The op3 (and)
field should be 000001, not 000000 as listed.
[Thanks to Nick Sorrell, University of Cincinnati]
(6) Page 121, Table 4.9: the cond field has a size of 4 bits, not 5 bits as
listed.
[Thanks to Prof. George Purdy, University of Cincinnati]
(7) Page 129, two-address instructions: 15 + 2 x 3 + 2 x 2 = 25, not 31 bytes.
[Thanks to Prof. George Purdy, University of Cincinnati]
(8) Section 4.2.3 "ARC Assembly Language Format": The book says immediate
constants are limited to 13 bits and the range it represents in two's
complement notation is -4196 to +4195. It should be -4096 to +4095.
(9) In homework problem 4.13, two of the load (ld) instructions are listed
with three arguments. This violates the recommended SPARC assembly language
syntax. Those instructions should be more like:
ld [%r1 + a], %r2
ld [%r1 + b], %r3
[Thanks to Prof. Bert Molenkamp, University of Twente, the Netherlands for
catching the next few errors.]
(10) Page 168, lines 6 and 7: the indices 19-21 and 22-24 are interchanged.
The SETHI bits are in positions 24-22 instead of 19-21, followed by the bits
in positions 21-19 of the IR (instead of 22-24).
(11) The microstore contents in Figure 5-17 are not correct at addresses 8, 9
and 10. Operand B is 100100 but is should be 100101 (IR).
(12) The microstore contents in Figure 5-17 are not correct at address 1688.
The jump condition should check on IR[13], and so the COND field should be
101 instead of 000. The correct code for address 1688 is then:
000000 0 000000 0 000000 0 0 0 0101 101 11010011010
(13) Chapter 6, p.203, line 6:
ld [ip], %r4 ! %r4 <- M[ip], which is addr of y
should read "which is addr of x". The next line should correspondingly be
changed from "M[y] <- 0" to "M[x] <- 0".
[Thanks to Prof. George Purdy, University of Cincinnati.]
(14) Page 118, Table 4.8: andcc is shown with an opcode of 010000 but it
should be 010001.
[Thanks to Robert Sikorski, University of Cincinnati.]
(15) Page 119, sll (shift left logical) instruction: the example usage is
incorrectly shown as srl (shift right logical). The example usage should be:
sll %r1, 3, %r2
"Shift %r1 left by three bits and store in %r2. Zeros are copied into the
three least significant bits of %r2."
[Thanks to Jacob Schlather, University of Cincinnati.]
(16) Page 252, srl (shift right logical) should have three arguments, not two
as shown. Replace:
srl %r3, %r5
with:
srl: %r3, 2, %r5
in two places.
[Thanks to Jacob Schlather, University of Cincinnati.]
(17) Pages 119 - 120, Example usage for "addcc %r1, 5, %r1" and "subcc %r1, 5,
%r1" both use the same meaning, "Meaning: Add 5 to %r1." The subcc example
should read "Meaning: Subtract 5 from %r1."
[Thanks to Donald Bledsoe.]
(18) Cache mapping schemes: On page 267:
"The line size is 64 bits (eight bytes.)"
should read:
"The line size is 256 bits (32 bytes.)"
On page 272, Figure 7-22, the line size should be 256 bits, not 64 bits as
listed.
[Thanks to Jason Corless.]
(19) Page 119: the description for sll is mostly copied from srl. The correct
text for sll is below:
Instruction: sll (op3 = 100101)
Description: Shift left logical. Shift a register to the left by 0 - 31 bits.
The vacant bit positions in the right side of the shifted register are filled
with 0's.
Example usage: sll %r1, 3, %r2
Meaning: Shift %r1 left by 3 bits and store in %r2. Zeros are copied into the
three least significant bits of %r2.
Object code: 10 0010 100101 00001 1 0000000000011
[Thanks to Prof. Sally Wood, Santa Clara University.]
(20) Page 82, figure 3-21: The multiplicand should be 14 (decimal) and the
multipler should be 21 (decimal). They are reversed in the figure.
[Thanks to Labrinus van Manen, via Prof. Bert Molenkamp, Univ. Twente,
the Netherlands.]
(21) On page 76, second calculation in Example 3-1:
.1011 * 10^7
- .0111 * 2^4
---------------
The intermediate result is: .1010001 *2^7.
The rounded result is .1011 * 2^7, but it should be .1010 *2^7.
[Thanks to Prof. Bert Molenkamp, Univ. Twente, the Netherlands.]
(22) In figure 5-2 (page 153) the given meaning of:
ORNCC is “Bitwise logical NOR”
This however, is not correct for the SPARC. The correct meaning is a bitwise A OR NOT(B).
[Thanks to Prof. Bert Molenkamp, Univ. Twente, the Netherlands.]
(23) ** Incorrect microprogram for instruction JMPL.
In the following usage:
jmpl %r8, %r15
The jmpl instruction should store the current %pc value in %r15 and transfer control to the address in %r8. However, the microcode as given on pages 165, 166, and 172 does not store the current %pc. [The ARCTool is correct, however.]
The current microprogram is:
/ JMPL
00000000000000000000000010110111011100010 / Is second source operand immediate? then goto 1762
00000010000001100000000100011000000000000 / Perform ADD on register sources -> goto 0
10010100000000100001000110000000000000000 / Get sign extended simm13 field
00000011000010100000000100011000000000000 / Perform ADD on register/simm13 sources -> goto 0
A correct version of the microprogram is:
10000000000000000000100100000000000000000 / Save %pc in %rd (R[rd]<-ADD(R[pc],R[0]))
10010100000000100001000110010111011100011 / R[temp0]<-SEXT(R[ir]); If second operand imm? then goto 1763;
00000000000001100001000100000000000000000 / R[temp0]<-R[rs2]
00000011000010100000000100011000000000000 / R[pc] <- R[rs1]+R[temp0]; goto 0
[Thanks to Marijn Mensinga and Jelle Evers, via Prof. Bert Molenkamp, Univ. Twente,
the Netherlands. Microcode by Prof. Molenkamp.]
(24) Slide 2-22: The calculation:
2 X ((3 - 4) + 1) X (8 - 1) X 8^(4-1) + 1
should be:
2 X ((3 - (-4)) + 1) X (8 - 1) X 8^(4-1) + 1
Note the "-(-4)" construct. This has been corrected in the PDF and PPT versions of the slides and is mentioned here for anyone who has the older versions.
[Thanks to William Lahti, Suffolk County Community College]
(25) Page 119, Section 4.2.7:
Instruction: sll (op3 = 100101)
Description: Shift left logical. Shift a register to the **left** by 0 - 31 bits. The vacant
bit positions in the **right** side of the shifted registers are filled with 0's.
Example usage: **sll** %r1, 3, %r2
Meaning: Shift %r1 **left** by three bits and store in %r2. Zeros are copied into the three least significant bits of %r2.
Same page, Instruction: sra (op3 - 100111):
Meaning: Shift %r1 right by three bits and store in %r2. **The MSB of %r1 is** copied into the three most significant bits of %r2.
[Thanks to Erik Kemp, University of Twente, the Netherlands]
(26) Appendix A, slide A-33:
The truth table is not the majority function, although the MUX inputs are correct for the function listed. If the truth table matched the majority function, which is shown in Slide A-32, then the MUX inputs should be 0, C, C, 1 from top to bottom. Also in slide A-33, the second C in the braces {0, 1, C, C} should have a bar over it.
[Thanks to William Lahti, Suffolk County Community College]
(27) Page 277:
The equation of effective access time is wrong; the time should be 80ns in the
equation instead of 8ns. The numerical result is correct, however.
[Thanks to Yi Wang.]
(28) Pages 390 and 426:
The diameter of a hypercube is log2N, not log2N - 1 as stated. The diameter is
the smallest number of hops to reach a node from any other. For a 2^4 = 16
node (4-space, to introduce that term) hypercube, the diameter is log2(16) =
4.
Problem 10.3: A 16-space hypercube has 2^16 nodes, and the diameter is
calculated as above.
[Thanks to Nicholas Beser.]