COMPUTER ARCHITECTURE AND ORGANIZATION: AN INTEGRATED APPROACH, 1/e -- ERRATA

Last updated: 6 October 2007

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(1) Figure 1-11 covering Moore's Law has an empty box in the middle of the
chart.  The box should be replaced with "Intel Processor Line" and should
appear below the plot, not on top of it.

(2) In section 4.2.3, on page 105 in the first paragraph under "The ARC 
Arithmetic and Logic Instructions", there is a reference to an example 
assembly instruction in Fig. 4-8 labeled "lab_3".  There is no corresponding 
instruction in the figure.

(3) On page 108 there are references to the "bz" and "bnz" instructions in 
several places (e.g., fig. 4-11 as well as the first full paragraph).  These 
appear to be inconsistent with the use of "be" and "bne" later in the chapter. 
The latter are the correct mnemonics for the book as they are also the ones 
the ARCTools simulator recognizes.  However, bz and bnz are equivalent to be 
and bne in the SPARC. 

(4) Section 4.2.3 "ARC Assembly Language Format": The book says immediate 
constants are limited to 13 bits and the range it represents in two's 
complement notation is -4196 to +4195. It should be -4096 to +4095.

(5) In homework problem 4.13, two of the load (ld) instructions are  listed 
with three arguments.  This violates the recommended SPARC assembly language 
syntax. Those instructions should be more like:

ld [%r1 + a], %r2
ld [%r1 + b], %r3