COMPUTER ARCHITECTURE AND ORGANIZATION: AN INTEGRATED APPROACH, 1/e -- ERRATA Last updated: 21 February 2010 ======================================== (1) Figure 1-11 covering Moore's Law has an empty box in the middle of the chart. The box should be replaced with "Intel Processor Line" and should appear below the plot, not on top of it. (2) In section 4.2.3, on page 105 in the first paragraph under "The ARC Arithmetic and Logic Instructions", there is a reference to an example assembly instruction in Fig. 4-8 labeled "lab_3". There is no corresponding instruction in the figure. (3) Page 107, Figure 4-10: The last instruction is: "st %r3 [z]" It should have a comma between arguments: "st %r3, [z]" [Thanks to Nick Sorrell, University of Cincinnati] (4) On page 108 there are references to the "bz" and "bnz" instructions in several places (e.g., fig. 4-11 as well as the first full paragraph). These appear to be inconsistent with the use of "be" and "bne" later in the chapter. The latter are the correct mnemonics for the book as they are also the ones the ARCTools simulator recognizes. However, bz and bnz are equivalent to be and bne in the SPARC. (5) Page 118, Table 4.7: The Field ID for simm13 should be 0xABB, and the corresponding object code should be 0101010101011 (13 bits). The op3 (and) field should be 000001, not 000000 as listed. [Thanks to Nick Sorrell, University of Cincinnati] (6) Page 121, Table 4.9: the cond field has a size of 4 bits, not 5 bits as listed. [Thanks to Prof. George Purdy, University of Cincinnati] (7) Page 129, two-address instructions: 15 + 2 x 3 + 2 x 2 = 25, not 31 bytes. [Thanks to Prof. George Purdy, University of Cincinnati] (8) Section 4.2.3 "ARC Assembly Language Format": The book says immediate constants are limited to 13 bits and the range it represents in two's complement notation is -4196 to +4195. It should be -4096 to +4095. (9) In homework problem 4.13, two of the load (ld) instructions are listed with three arguments. This violates the recommended SPARC assembly language syntax. Those instructions should be more like: ld [%r1 + a], %r2 ld [%r1 + b], %r3 [Thanks to Prof. Bert Molenkamp, University of Twente, the Netherlands for catching the next few errors.] (10) Page 168, lines 6 and 7: the indices 19-21 and 22-24 are interchanged. The SETHI bits are in positions 24-22 instead of 19-21, followed by the bits in positions 21-19 of the IR (instead of 22-24). (11) The microstore contents in Figure 5-17 are not correct at addresses 8, 9 and 10. Operand B is 100100 but is should be 100101 (IR). (12) The microstore contents in Figure 5-17 are not correct at address 1688. The jump condition should check on IR[13], and so the COND field should be 101 instead of 000. The correct code for address 1688 is then: 000000 0 000000 0 000000 0 0 0 0101 101 11010011010 (13) Chapter 6, p.203, line 6: ld [ip], %r4 ! %r4 <- M[ip], which is addr of y should read "which is addr of x". The next line should correspondingly be changed from "M[y] <- 0" to "M[x] <- 0". [Thanks to Prof. George Purdy, University of Cincinnati.] (14) Page 118, Table 4.8: andcc is shown with an opcode of 010000 but it should be 010001. [Thanks to Robert Sikorski, University of Cincinnati.] (15) Page 119, sll (shift left logical) instruction: the example usage is incorrectly shown as srl (shift right logical). The example usage should be: sll %r1, 3, %r2 "Shift %r1 left by three bits and store in %r2. Zeros are copied into the three least significant bits of %r2." [Thanks to Jacob Schlather, University of Cincinnati.] (16) Page 252, srl (shift right logical) should have three arguments, not two as shown. Replace: srl %r3, %r5 with: srl: %r3, 2, %r5 in two places. [Thanks to Jacob Schlather, University of Cincinnati.] (17) Pages 119 - 120, Example usage for "addcc %r1, 5, %r1" and "subcc %r1, 5, %r1" both use the same meaning, "Meaning: Add 5 to %r1." The subcc example should read "Meaning: Subtract 5 from %r1." [Thanks to Donald Bledsoe.]