PRINCIPLES OF COMPUTER ARCHITECTURE, 1/e -- ERRATA
Last updated: 31 October 2004
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(1) Section 7.3.1 and A.4.2 headings have incorrect capitalizations in the Table
of Contents.
(2) The first sentence on page 1, Chapter 1, Section 1.1 should read: "Computer
architecture deals with..."
It currently says: "Computer architecture deas with..."
(3) Page 26, the formula 2^K = ix5^K/(2^K x 5^K)
should be i / 2^K = ix5^K/(2^K x 5^K).
(4) Page 51. The 2C entry should be a comma, ",".
(5) Page 66, Figure 3-4: the output diff_i of the full subtractor is labeled
as (a_i-b_i), but it should be ((a_i-bor_i) - b_i).
(6) Page 68, Figure 3-9: The one's complement representation of (-1.0)_10
is malformed, and should be 1110.1 instead of 1110.0. Further, the
description of one's complement signed addition that refers to
Figure 3-9 is incorrect. The end-around carry should be added into
the *least significant bit*, as opposed to the 1's position as stated.
(7) Page 76, the equation for C4 is truncated.
(8) Page 104: The second to last line in the first paragraph reads:
"format, from 00000000H to FFFFFFFFFH"
which incorrectly shows nine F's instead of eight.
(9) The solutions to the Chapter 4 exercises use macros without defining them
before their first use. The macros, and their expansions, are:
mov N,%rDst
is the same as :
orcc %r0, N, %rDst
and
jmp %rReg+M
is the same as:
jmpl %rReg+M, %r0
(10) Page 163, Section 5.2.1, "Notice that the i bit is used to distinguish
between the first memory format (i = 0) and the second (i = 0). Therefore,
the i bit is set to 1."
should read: "and the second (i = 1)."
(11) Page 170, Figure 5-6: a line should be added before sub returns,
such as addcc %2, %3, %3. As it is, the subroutine only inverts y.
(12) Note (this not an error, but a clarification): Fig 5-8 and also problem 5.8
use #nnnnnnnn for immediate values -- the syntax of some assemblers, but not of
the ARC or the Sun 'as' assemblers, which just use nnnnn or 0xnnnnnnnn.
(13) Page 206, line 44 of the microcode: this is not an error, but a
suggestion for a simplification: Use R[rd] instead of R[0], and then the
prior shifting lines can be removed.
(14) Page 221 in Chapter 6,
Paragraph starting with "A similar ...":
"... statement 3 returns to statement 1 unconditionally"
should be:
"... statement 3 returns to statement 0 unconditionally"
(15) On page 223/224, in the HDL code line 19, the pc is incremented by
adding to the value in temp0. However, at no point before line 19, in
this logic line (0 -> 1 -> 2-> 19) has the value disp22 * 4 been loaded
loaded into temp0.
An additional 2 states are required:
temp0 <- ADD(ir,ir). !disp22 * 2
temp0 <- ADD(temp0,temp0). !disp22 * 4
In addition, line 6 should read:
temp0 <- ADD(temp0,temp0)
(because simply adding ir will just overwrite the old value.)
(16) Page 266, Figure 7-18, the last line in the table should be:
80ns x 144ns = 11,520ns
instead of:
80ns x 144ns = 12,240ns.
(17) Page 330, in Section 8.5.4 covering optical disks, the
original speed of rotation is 30 RPM,
which is *not* the same as the 300 RPM of a floppy disk.
(18) Page 369, The right side of the formula in the example of k = 7 should
be 2^(r+1) where (r+1) should be in superscript. As it is, it appears
as 2r + 1.
The solution of r=7 is still correct, but the equation needs to be
corrected. For reference, here are the simplification steps:
2^k x [(k+r) + 1/2(k+r)(k+r-1) + 1] <= 2^(k+r)
2^k x [(k+r) + 1/2(k+r)(k+r-1) + 1] <= (2^k)(2^r)
(k+r) + 1/2(k+r)(k+r-1) + 1 <= 2^r
(k+r) + 1/2(k+r)(k+r-1) + 1 <= 2^r
k + r + 1/2(k^2 + kr -k + kr + r^2 - r) + 1 <= 2^r
k + r + 1/2(k^2 + 2kr -k -r + r^2) + 1 <= 2^r
substituting k=7:
7 + r + 1/2(7^2 + 14r - 7 - r + r^2) + 1 <= 2^r
8 + r + 1/2(49 - 7 + 13r + r^2) <= 2^r
8 + r + 1/2(42 + 13r + r^2) <= 2^r
8 + r + 21 + (13/2)r + (1/2)r^2<= 2^r
29 + (15/2)r + (1/2)r^2 <= 2^r
29 + (15/2)r + (1/2)r^2 <= 2^r
r^2 + 15r + 58 <= 2^(r+1)
The smallest value of r that satisfies the relationship is r=7:
r=7: 49 + 105 + 58 <= 2^8 TRUE
(19) Page 395, the simplified formula expressing the average cycles per
instruction (CPI) should be:
CPIavg = 1 + bP_bP_t
In the book, the b - branch penalty is missing from the second term.
(20) Page 424, Figure 10-23: Operation 2 should be:
temp2 = temp0 + temp1
not
temp2 = temp1 + temp2
(21) Page 450, Figure A-11, the first line of the truth
table on the left hand side, the value for A should be zero instead of the
disable state sign.
(22) Page 473 and Page 476, in Figure A.42, the timing behavior for the
S-R flip-flop is such that after S=1, that
+2Delta_t, Q=1
and
+2Delta_t the S-R flip-flop is stable (the outputs have opposite values)
and after R=1, that
+Delta_t, Q=0
and
+2Delta_t, the S-R flip-flop is stable
In Figure A.46 (Clocked S-R Flip-Flop), the timing is shown as the same
of Figure A.42 (after CLK = 1), but signals have to "go through" the
AND gates. Even if the AND gates do not have same delay as
the NOR gates, they do have a delay, and thus the timings
are a little bit longer than those of the simple S-R flip-flop.
(23) Page 473, Figure A-43: in the second configuration, the two bubbles
at the outputs of the AND-gates should not be there. The inversion of an
OR-gate is equivalent to an AND-gate with inversed inputs.
(24) Page 476, regarding timings of the Clocked D Flip-Flop: the delay of the
AND gates are included as being Delta_t (the same delay as NOR gates.)
Even when Figure A-47 is right in that sense, it is necessary
that the clock should become 1 after D has become 0 some time later for the
NOT gate to produce 1. Otherwise, the following incorrect timing behavior
would be possible (assuming all the gates have the same delay of Delta_t,
A1 is the output of the AND gate of D and CLK and A2 is the output of the
other AND gate):
If D and CLK change simultaneously enough, 3Delta_t are necessary for the
Clocked D Flip-Flop to become stable when D becomes 0 and 4Delta_t are
necessary when D becomes 1.
(25) Page 478, Figure A-49, the buffer should be removed from the
clock input of the J-K flip-flop because it can cause a timing
problem from the delay that it introduces to only one of the
AND gate inputs.
(26) Page 478, Figure A-50, the positions of Q and Q_bar are reversed as
compared with the circuit as a notational convenience. (It is not an
error but needs this explanation.) Also, Figure A-50 has a similar
delayed clock issue to Figure A-49.
(27) Page 480, Figure a-53: the outputs q0 and q1 are incorrectly reversed in
the figure.
(28) Page 490, Figure A-69: the shift-right input incorrectly appears
twice on both the
schematic as well as the chip diagram. The signal labeled "shift right input"
in the upper right of the figure should be "shift left input", and the
signal labeled "shift right input" on the right side of the chip diagram
should be labeled "shift left input".
(29) Page 491, Figure A-70, for the leftmost flip-flop (output Q2), which
outputs the most significant bit, not only the output from the second
but also the output from the third flip-flop should be ANDed with CLK and EN.
There should be an additional input line from the output from the rightmost
flip-flop to the most left AND-gate (or alternatively an
intermediate AND-gate that receives inputs from the outputs of the two
flip-flops on the right side).
(30) Page 538, Figure B-44(b), the state assignment for
the implementation of the majority function for the J-K flip-flop:
the assignment for B' should be 010/0 if X=0 and 101/0 if X=1
Also, the corresponding MUX to flip-flop mapping in Figure B-45 should
be changed to correspond.
(31) orn and orncc are incorrectly defined in the text. According to the
SPARC reference manual, orn is defined as "a or (not b)," as distinct from
nor which implements the conventional nor function. The book covers
orn and orncc as if they are nor. While this may not have a great impact
on instruction, it creates a discrepancy between the description of
orncc in the book, the ARCTools suite, and the SPARC reference materials.
(32) Powerpoint slide 2-23: the formula should be (3 - (-4) +1).
(33) Powerpoint slide Slide 3-22: The first pin in the 4-input AND gate
is going to G2 but should be going to P3 instead. This is also an
error in the corresponding figure in the book (page 78, Figure 3-17.)
(34) Section 6.3, Hardwired Control, Figure 6-24: it is not possible
to select temp0 because A[0] = A[2], but A[0] and A[2] need to differ
to select temp0 (register 33):
A[5] = 1
A[4] = 0
A[3] = 0
A[2] = 0
A[1] = 0
A[0] = 1
Also, in line 10 of the hardwired microcode (Figure 6-22), there is SEXT13
but CS10 is not in the logic function of ALU[3] in Figure 6-24.
(35) The equation on page 361 should be labelled 9.1, not 8.1.